module IDEX(
    input clk, rst, 
    input JALFlush_from_WB,   // flush IDEX regiater
    input PCScr_from_MEM,

    // control signals
    input branch_beq_from_ID, branch_bne_from_ID,      // work at MEM
    input JALFlush_from_ID,                            // work at WB

    input ALUSrc_from_ID, RegDst_from_ID,              // work at EX 
    input [2:0] ALUop_from_ID,                         // work at EX
    input SignSelect_from_ID,
    input MemWrite_from_ID, MeMRead_from_ID,           // work at MEM   
    input RegWrite_from_ID, MeMtoReg_from_ID,          // work at WB
    // data
    input [31:0] pc4_from_ID,                  // pc+4
    input [31:0] inst_from_ID,                 // instruction
    input [31:0] Ext_imm_from_ID,              //sign extend value
    input [31:0] Ext_zero_from_ID,
    input [31:0] Data_from_rs, Data_from_rt,   // data from regs 
    input [31:0] JalAddr_from_ID,                 //work at WB

    // output
    output reg branch_beq_2_EX, branch_bne_2_EX,     // work at MEM
    output reg JALFlush_2_EX,                        // work at WB

    output reg ALUSrc_2_EX, RegDst_2_EX,               // work at EX 
    output reg [2:0] ALUop_2_EX,                       // work at EX
    output reg SignSelect_2_EX,                             // work at EX

    output reg MemWrite_2_EX, MeMRead_2_EX,            // work at MEM   
    output reg RegWrite_2_EX, MeMtoReg_2_EX,           // work at WB

    output reg [31:0] pc4_2_EX,                        // pc+4
    output reg [31:0] inst_2_EX,                       // instruction
    output reg [31:0] Ext_imm_2_EX,                    //sign extend value
    output reg [31:0] Ext_zero_2_EX,
    output reg [31:0] Data_2_rs, Data_2_rt,             // data from regs 
    output reg [31:0] JalAddr_2_EX
);


always@(posedge clk or negedge rst)begin
    if(!rst)begin
        branch_beq_2_EX <= 1'b0; 
        branch_bne_2_EX <= 1'b0;     
        JALFlush_2_EX <= 1'b0;        // branch instruction

        ALUSrc_2_EX <= 1'b0;
        RegDst_2_EX <= 1'b0; 
        SignSelect_2_EX <= 1'b0;                    
        MemWrite_2_EX <= 1'b0; 
        MeMRead_2_EX <= 1'b0;            
        RegWrite_2_EX <= 1'b0; 
        MeMtoReg_2_EX <= 1'b0;
        pc4_2_EX <= 32'd0;                  
        inst_2_EX <= 32'd0;                       
        Ext_imm_2_EX <= 32'd0; 
        Ext_zero_2_EX <= 32'b0;                  
        Data_2_rs <= 32'd0; 
        Data_2_rt <= 32'd0; 
        JalAddr_2_EX <= 32'b0;              
        ALUop_2_EX <= 3'b011;  
    end
    else if(JALFlush_from_WB|PCScr_from_MEM)begin
        branch_beq_2_EX <= 1'b0; 
        branch_bne_2_EX <= 1'b0;     
        JALFlush_2_EX <= 1'b0;        // branch instruction

        ALUSrc_2_EX <= 1'b0;
        RegDst_2_EX <= 1'b0; 
        SignSelect_2_EX <= 1'b0;                    
        MemWrite_2_EX <= 1'b0; 
        MeMRead_2_EX <= 1'b0;            
        RegWrite_2_EX <= 1'b0; 
        MeMtoReg_2_EX <= 1'b0;
        pc4_2_EX <= 32'd0;                  
        inst_2_EX <= 32'd0;                       
        Ext_imm_2_EX <= 32'd0; 
        Ext_zero_2_EX <= 32'b0;                  
        Data_2_rs <= 32'd0; 
        Data_2_rt <= 32'd0; 
        JalAddr_2_EX <= 32'b0;              
        ALUop_2_EX <= 3'b011; 
    end
    else begin
        branch_beq_2_EX <= branch_beq_from_ID; 
        branch_bne_2_EX <= branch_bne_from_ID;     
        JALFlush_2_EX <= JALFlush_from_ID;
        ALUSrc_2_EX <= ALUSrc_from_ID;
        RegDst_2_EX <= RegDst_from_ID; 
        SignSelect_2_EX <= SignSelect_from_ID;                    
        MemWrite_2_EX <= MemWrite_from_ID; 
        MeMRead_2_EX <= MeMRead_from_ID;            
        RegWrite_2_EX <= RegWrite_from_ID; 
        MeMtoReg_2_EX <= MeMtoReg_from_ID;
        pc4_2_EX <= pc4_from_ID;                  
        inst_2_EX <= inst_from_ID;                       
        Ext_imm_2_EX <= Ext_imm_from_ID;  
        Ext_zero_2_EX <= Ext_zero_from_ID;                
        Data_2_rs <= Data_from_rs; 
        Data_2_rt <= Data_from_rt;  
        JalAddr_2_EX <= JalAddr_from_ID;              
        ALUop_2_EX <= ALUop_from_ID; 
    end
end
endmodule